PIC16F87T-E/ML【PDF 155/200 页】IC MCU FLASH 4KX14 EEPROM 28QFN

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8008H–AVR–04/11

ATtiny48/88

9.3.5

PCIFR – Pin Change Interrupt Flag Register

Bits 7:4 – Res: Reserved Bits

These bits are reserved and will always read zero.

Bit 3 – PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT[27:24] pin triggers an interrupt request, PCIF3 becomes set

(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit 2 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit 1 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT[15:8] pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit 0 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

9.3.6

PCMSK3 – Pin Change Mask Register 3

Bits 7:4 – Res: Reserved Bits

These bits are reserved and will always read zero.

Bits 3:0 – PCINT[27:24]: Pin Change Enable Mask 27:24

Each PCINT[27:24] bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT[27:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on

the corresponding I/O pin. If PCINT[27:24] is cleared, pin change interrupt on the corresponding

I/O pin is disabled.

Bit

76543

210

0x1B (0x3B)

––––

PCIF3

PCIF2

PCIF1

PCIF0

PCIFR

Read/Write

R/W

Initial Value

00000

000

Bit

(0x6A)

––

PCINT27

PCINT26

PCINT25

PCINT24

PCMSK3

Read/Write

R/W

Initial Value

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